Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits
نویسندگان
چکیده
منابع مشابه
A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits
This paper mainly presents Mixed Gate Diffusion Input Full Adder based on static CMOS inverter topology. In this proposed mixed Full Adder topology, GDI Full adders are followed by inverters in the long Full Adder chain to improve the performances as compared to conventional single topology Full adder chain. For any circuits reducing the speed and power dissipation are the important constraints...
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The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Sourc...
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VLSI technology has developed over the years thereby enhancing the performance of chips in terms of three basic constraints viz. delay, power and area. Gate Diffusion Input technique is one such method which attempts to minimize the delay and power consumed by the circuit. The paper basically focuses on the implementation of the technique on combinational logic circuits and experimental delay r...
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Gate Diffusion Input (GDI) is a technique for designing low power circuits. This technique allows usage of less number of transistors as compared to CMOS logic. The basic GDI cell consists of only two transistors which are used to implement the basic logic functions. Because of less number of transistors, the switching is reduced and hence there will be a less power, delay and also reduced area...
متن کاملDesign of Power-Efficient Digital Circuits Using Gate-Diffusion Input (GDI) Technique in CMOS Process
in this paper Gate diffusion input (GDI) technique of Low-power digital circuit design is described and verified in 0.18μm CMOS process. This technique permits reducing power consumption, propagation delay, and area of digital circuits of logic design. Performance comparison with traditional CMOS and pass-transistor logic design techniques is presented. These methods are compared with respect t...
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ژورنال
عنوان ژورنال: Procedia Technology
سال: 2012
ISSN: 2212-0173
DOI: 10.1016/j.protcy.2012.10.010